The invention relates to plastic encapsulated multichip hybrid integrated circuit structures, particularly those suitable for a combination of high power chips and low power chips, and to methods for manufacturing such plastic encapsulated multichip hybrid integrated circuits.
Hybrid integrated circuits have been widely manufactured for many years to provide, in a single package, electronic devices that are too complex to be economically integrated on a single monolithic semiconductor chip. In hybrid integrated circuits, various monolithic integrated circuit chips, capacitors, film resistors, and other components are die bonded, deposited, or otherwise attached to a ceramic substrate. The ceramic substrate has thereon a suitable metal interconnection pattern including "flag" areas (onto which integrated circuit chips and other components are bonded) and also including metal interconnect strips ("interconnects") to which bonding pads of the various components are electrically connected by wire bonding techniques. External leads of a hybrid integrated circuit package are electrically connected to the ceramic substrate in various ways. Until recently, hybrid integrated circuits generally were quite expensive. It has been believed that the market for hybrid integrated circuits could be greatly expanded if the costs of hybrid integrated circuit assembly and encapsulation techniques could be substantially lowered. To this end, multiple integrated circuit chips have been provided by bonding them to a metalization pattern on a thin insulating layer formed as part of a flexible ribbon substrate attached to a conventional lead frame. Bonding pads of the various integrated circuit chips and other components have been wire bonded to metal strips or interconnects on the insulating layer and to fingers of the lead frame. The assembly has been encapsulated in plastic by a plastic transfer molding process. This technique is disclosed in Japanese Patent Public Disclosure No. 60-41249, dated Mar. 4, 1985, assigned to NIPPON DENKI K. K. The technology disclosed in that reference provides lower cost, complex hybrid integrated circuits, but is subject to the limitation that the integrated circuit chips therein must dissipate only relatively low amounts of power. This is necessary because flexible ribbon-type materials that are good electrical insulators are relatively poor thermal conductors. Since the etched copper technology requires gold electroplated interconnects, widespread use of vias and connections of the vias to inner, isolated interconnects are necessary to provide connection of isolated interconnects to a "plating bus". These vias and connections thereto add expense, and also degrade electrical performance, as subsequently explained. Therefore, if high power, high speed, low noise, low cost bipolar integrated circuit chips or other high power discrete or integrated circuit chips all are required to implement a desired hybrid integrated circuit, the structure and technique disclosed in the above Japanese reference is inadequate and impractical.
As those skilled in the art know, if a hybrid integrated circuit is to be encapsulated in plastic using a plastic transfer molding process, the flow of plastic produces substantial stress on chip-to-chip wire bonds and on chip-to-lead-frame wire bonds. This makes it almost essential to use gold bonding wire in plastic encapsulated integrated circuits, since the more ductile characteristics of the gold bonding wires enable it to withstand the flow of plastic during the transfer molding process. However, chip-to-chip wire bonding is very difficult to accomplish using gold bonding wire. Usually, chip-to-chip bonds require a "wedge bond", rather than a "capillary bond". Wedge bonds are more adaptable to aluminum rather than gold wire. When capillary bonding techniques are used, short, isolated metal strips or "interconnects" usually are required.
An example of a hybrid integrated circuit that would be very difficult to provide in a plastic package using the prior technology disclosed in Japanese Patent Public Disclosure No. 60-41249 is a digital to analog converter including a relatively low power CMOS integrated circuit chip containing digital logic circuitry and switching circuitry and a relatively high power bipolar integrated circuit chip containing an analog amplifier and bit current switch circuits. Up to now, such a hybrid integrated circuit digital to analog converter encapsulated in plastic could be provided only by die bonding both the CMOS chip and the bipolar chip onto a multilayer polymer film substrate attached to a lead frame. The latter approach is more costly than desired, and results in a lower level of circuit performance than is desirable, either because of 1) the high parasitic capacitance associated with the vias and connections thereto and/or 2) lower operating speeds than might otherwise be achieved since the chip power dissipation is limited by the high thermal resistance of the polymer film, and speed often is limited by the amount of power dissipation that can be allowed.
It would be desirable to provide a much lower cost multichip hybrid integrated circuit including both high power chips (such as bipolar integrated circuit chips) and high density, low power integrated circuit chips (such as integrated circuit CMOS logic chips) in a single, low cost, plastic-encapsulated hybrid integrated circuit package.
Some prior multichip plastic encapsulated integrated circuits which include a plurality of integrated circuit chips are die bonded onto conductive flags formed on a plastic substrate. Manufacture of such substrates has included provision of vias (i.e. feedthroughs) extending through the plastic substrate to metal "plating bus" conductors on the bottom surface of the plastic substrate to enable all conductors, (including "interior" interconnects entirely surrounded by other conductors) on the top surface to be electrically shorted to a plating bus to which an electroplating voltage is applied during gold electroplating. The vias and connections thereto add to the expense of manufacture, as they require substantial additional surface area and complicate the interconnect routing. When the insulative substrate with the electroplated conductors thereon is punched out of the ribbon substrate, the interconnects are severed from the plating bus. The vias and the additional conductors connected thereto (on the bottom side of the substrate) cause additional capacitive loading on various circuit nodes, slowing electrical circuit operation. The extra conductive lines connected to the vias also may produce undesired electrical coupling and noise pickup. If vias are not used, additional "temporary" shorting bars are required to connect each interconnect to the plating bus. Such shorting bars must be removed by machining a groove in the surface of the insulative film after the electroplating process. This groove then must be bridged by additional wire bonds, increasing overall costs.